(1) Field of the Invention
The present invention relates to a method and apparatus for converting multimegabit-rate data into asynchronous transfer mode (ATM) cells and vice versa, the ATM cells being transmitted in an asynchronous transfer mode.
A broadband integrated services digital network (B-ISDN) which provides a multimegabit-rate data communications service is proposed, and an asynchronous transfer mode (ATM) for use with the B-ISDN to realize such a data communications service is known. In the asynchronous transfer mode, an ATM cell contains 53 bytes of information: a 5-byte header and a 48-byte data field, and such ATM cells are transmitted at a rate of several megabits per second.
Multimegabit-rate data communications interfaces which are currently used include a frame relay (FR) interface with a transmission rate around 2 Mbps (megabits per second), a switched multimegabit data services (SMDS) interface with a transmission rate around 45 Mbps, and digital signal-level 1, 2 and 3 (DS1, DS2 and DS3) interfaces with transmission rates 1.544 Mbps, 6.312 Mbps and 44.736 Mbps. It is proposed to unify these interfaces into an ATM interface for use with the B-ISDN so that the unified ATM interface will provide a high transmission rate above 600 Mbps for multimegabit-rate data communications services. To realize this, it is desired to provide an ATM conversion method which is capable of efficiently converting multimegabit-rate data into ATM cells and vice versa for use with the unified ATM interface.
(2) Description of the Related Art
FIG. 1 shows an asynchronous transfer mode (ATM) terminal which includes the above-mentioned data communications interfaces.
Referring to FIG. 1, an ATM terminal 52 is linked to a switching system 51 for the B-ISDN. The ATM terminal 52 includes an ATM-UNI (asynchronous transfer mode--user network interface) control unit 54, a service interface unit 53, and a common unit 55. A maintenance unit 56 is externally connected with the ATM terminal 52 via the common unit 55. The common unit 55 is connected to the service interface unit 53.
In the ATM terminal 52, shown in FIG. 1, the service interface unit 53 includes a SMDS (switched multimegabit data service) interface 53a, a FR (frame relay) interface 53b, a DS (digital signal--levels 1-3) interface 53c, etc. The common unit 55 includes a processing unit. Each of the above interfaces of the service interface unit 53 is controlled by the common unit 55. A SMDS terminal 57 is connected to the ATM terminal 52 via the SMDS interface 53a. A FR terminal 58 is connected to the ATM terminal 52 via the FR interface 53c. A DS terminal 59 is connected to the ATM terminal 52 via the DS interface 53c. Also, the other user terminals may be connected to the ATM terminal 52.
From the aspect of the switching system 54, the ATM terminal 52 is taken as one of a plurality of terminals on the B-ISDN network. The ATM terminal 52 is connected with the switching system 51 via the ATM-UNI control unit 54. The above-mentioned terminals, including the SMDS terminal 57, the FR terminal 58 and the DS terminal 59, are connected to the ATM terminal 52 via the service interface unit 53. Each of the interfaces of the ATM terminal 52 is controlled by the common unit 55. Therefore, the data communications service multiplexing is performed by the ATM terminal 52, and the unified ATM interfacing and switching is performed by the switching system 51.
FIG. 2 shows a part of the ATM terminal 52 which performs procedures for converting SMDS slots into ATM cells and vice versa. Referring to FIG. 2, a physical layer control unit 61, a PLCP layer control unit 62, a SMDS-ATM converting unit 63, and an ATM-UNI control unit 64 are linked. This ATM-UNI control unit 64 corresponds to the ATM-UNI control unit 54 in FIG. 1. The physical layer control unit 61 corresponds to the SMDS terminal 57 connected to the ATM terminal 52 in FIG. 1.
Also, a relationship between a SMDS slot and an ATM cell is shown in FIG. 2. The SMDS slot contains a 7-byte SMDS header and a 46-byte SMDS data field. The SMDS header includes a 1-byte address control field (ACF), 3-byte network control information (NCI), a 1-byte header check sequence (HCS), and a 2-byte descriptor field. The descriptor field includes a set of segment type (ST) bits, a set of sequence number (SN) bits, and a set of message identifier descriptor (MID) bits.
The ACF of the SMDS slot includes a busy bit (B) at the most significant digit. This busy bit is indicative of whether the SMDS slot is used for data communication. The SMDS data field of the SMDS slot includes a 44-byte payload segmentation unit (SU) and a 2-byte remaining unit. The remaining unit includes a set of payload length (PL) bits and a set of payload cyclic redundancy check (CRC) bits.
The ATM cell, as shown in FIG. 2, contains a 5-byte ATM header and a 48-byte ATM data field. The ATM header includes a 4-bit general flow control (GFC), an 8-bit virtual path identifier (VPI), a 16-bit virtual channel identifier (VCI), a 3-bit payload type (PT), a 1-bit cell loss priority (CLP), and an 8-bit header error control (HEC).
In the case of the ATM adaptation layer (AAL) type 3/4, the ATM data field of the ATM cell includes a 2-byte descriptor field, a 44-byte segmentation and reassembly sublayer payload service data unit (SDU), and a 2-byte remaining unit. The descriptor field includes segment type (ST) bits, sequence number (SN) bits, and message identifier descriptor (MID) bits. The remaining unit includes payload length (PL) bits and payload cyclic redundancy check (CRC) bits.
As described above, the SMDS-ATM converting unit 63 converts the SMDS slots from the SMDS terminal 61 into the ATM cells, and the ATM cells from the SMDS-ATM converting unit 63 are transferred to the ATM-UNI control unit 64. More specifically, in this SMDS-ATM converting procedure, the ACF, the NCI and the HCS (which are a total of 5 bytes) of the SMDS header are converted into the GFC, the VPI, the VCI, the PT, the CLP and the HEC (which are a total of 5 bytes) of the ATM header. The remaining elements (the ST, the SN, the MID, etc.) of the SMDS slot are not converted but are inserted as the corresponding elements (the ST, the SN, the MID, etc.) of the ATM cell. Thus, the SMDS-ATM converting unit 63 produces the ATM cell from the SMDS slot as shown in FIG. 2.
On the other hand, when the SMDS slot is transmitted from the ATM terminal 52 to the SMDS terminal 57, the SMDS-ATM converting unit 63 converts the ATM cell from the ATM-UNI control unit 64 into the SMDS slot. In the case of the AAL type 3/4, the 5-byte conversion portion (the GFC, the VPI, the VCI, the PT, the CLP and the HEC) of the ATM cell are converted into the ACF, the NCI and the HCS of the SMDS header. The ST, the SN and the MID of the ATM cell are not converted but are inserted as the corresponding elements (the ST, the SN and the MID) of the SMDS slot. The SDU, the PL and the CRC of the ATM cell are not converted but are inserted as the corresponding elements (the SU, the PL and the CRC) of the SMDS slot.
The elements of the SMDS header and the elements of the ATM header are different from each other, but the total length of the SMDS slot and the total length of the ATM cell are the same. The conversion from the ATM header into the SMDS header is performed based on predetermined menu values, and the result of the error calculation of the header error control (HEC) of the ATM header is inserted as the header check sequence (HCS) of the SMDS header.
FIG. 3 shows a part of the ATM terminal which performs procedures for converting the FR data into the ATM cells and vice versa. Referring to FIG. 3, a Q.922 core layer control unit 71, an ATM cell assembly and disassembly unit 72, and an ATM-UNI control unit 73 are linked. This ATM-UNI control unit 73 corresponds to the ATM-UNI control unit 54 in FIG. 1. Q.922 is the number of the CCITT recommendation, and the Q.922 core layer control unit 71 carries out the processing between the unit 71 and the FR terminal based on the essential parts of the data-link layer protocol.
Also, a relationship between the FR data and the ATM cells is shown in FIG. 3. The format of the frame relay data is similar to the format of the High-level Data Link Control Procedure (HDLC). As shown in FIG. 3, the FR data includes a flag (F), an address portion, a user data portion, a frame check sequence (FCS), and a flag (F), and a frame is constituted by these elements of the FR data. The address portion includes a data link connection identifier (DLCI).
FIGS.4A, 4B and 4C are diagrams for explaining the address portion of the frame relay data. FIG. 4A shows a two-octet address portion, FIG. 4B shows a three-octet address portion, and FIG. 4C shows a four-octet address portion. As shown, the address portion of the FR data includes the data link connection identifier (DLCI), an EA (extended address field) bit, a C/R (command/response) bit, a FECN (forward direction congestion notice) bit, a BECN (backward direction congestion notice) bit, a DE (disregard indicator) bit, and a D/C (DLCI/DL core control indicator) bit.
The DLCI identifier is 10 bits of information for data link connection identification. As the content of this DCLI identifier, 0 is used to indicate an in-channel signal, 1-15 are reserved, 16-511 are used to support user data by a channel other than the D-channel, 512-991 are used to identify a logical link for supporting user data, 992-1007 are used to indicate a data-link layer management of the frame mode bearer service, 1008-1022 are reserved, and 1023 is used to indicate an in-channel data-link layer management.
As shown in FIG. 3, when converting the FR data into the ATM cells, the elements (the address portion and the user data portion) of each frame of the FR data, other than the flags (F) and the FCS, are converted into body portions of the ATM cells. An ATM header (HD) is added to each of the ATM cells. On the other hand, when converting the ATM cells into the FR data, the body portions of the ATM cells (the headers (HD) are deleted) are assembled into the FR data, the result of calculation of the frame check sequence (FCS) is inserted to the FCS of the FR data, and the flags (F) are added to the FR data.
FIG. 5 shows a part of the ATM terminal which performs procedures for converting the DS data into the ATM cells and vice versa. Referring to FIG. 5, a physical layer control unit 81, an ATM cell assembly and disassembly unit 82, and an ATM-UNI control unit 83 are linked. This ATM-UNI control unit 83 corresponds to the ATM-UNI control unit 52 in FIG. 1. User terminals are connected to the physical layer control unit 81, and the digital signals DS1 (1.544 Mbps), DS2 (6.312 Mbps) and DS3 (44.736 Mbps) are transmitted and received between the user terminals and the physical layer control unit 81.
Also, a relationship between the DS data and the ATM cells is shown in FIG. 5. The ATM cell assembly and disassembly unit 82 converts the DS data into the ATM cells and converts the ATM cells into the DS data.
When converting the DS data from the DS terminal 58 into the ATM cells for the switching system 51, the DS data is divided into a plurality of 47-byte segments. An ATM header (HD) is added to the top of each of the segments of the DS data, and 1-byte payload cyclic redundancy check (CRC) bits are added to the bottom of each segment of the DS data. The ATM header, one segment of the DS data, and the CRC bits form an ATM cell including 53 bytes of information. The ATM cells are thus produced by disassembling the DS data and adding the ATM header and the CRC bits. These ATM cells are transmitted to the switching system 51 via the ATM-UNI control unit 83.
When converting the ATM cells from the switching system 51 into the DS data for the DS terminal 59, the ATM header (HD) and the payload cyclic redundancy check (CRC) bit are removed from each of the ATM cells. The DS data is produced by assembling the remaining elements of the ATM cells.
The above SMDS, FR and DS data communications services are among the multimegabit-rate data communications services which are currently used. However, it is difficult to unify the SMDS, FR and DS services into the narrowband-ISDN (N-ISDN) services since the N-ISDN uses low transmission rates only. Therefore, it is proposed to unify these services into the B-ISDN services using the above ATM interface which provides a high transmission rate above 600 Mbps for the multimegabit-rate data communications services.
However, the above-described ATM conversion procedures take into account converting all the multimegabit-rate data into the ATM cells, regardless of whether the data is effective or ineffective. Even when the data is ineffective, the above ATM conversion procedures perform converting the data into the ATM cells, and such ATM cells are transmitted. Therefore, the efficiency of the ATM conversion of the above procedures is not adequate for the multiplexing of the SMDS, FR and DS data communications services.
It is difficult to efficiently convert multimegabit-rate data into ATM cells and vice versa with the above-mentioned ATM terminal including the multiple service interfaces.